1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and more particularly a Delay Locked Loop (DLL) circuit for generating an internal clock of a semiconductor integrated circuit.
2. Related Art
A conventional DLL circuit provides an internal clock signal having a phase that leads the phase of a reference clock signal obtained by converting an external clock signal. The DLL circuit is used to solve a problem in that as an internal clock signal used in a semiconductor integrated circuit is delayed through a clock signal buffer and a transmission line, a phase difference appears between the internal clock signal and the external clock signal. As a result, an output data access time becomes longer. The DLL circuit controls the internal clock signal such that the phase of the internal clock signal appears at a predetermined time prior to the external clock signal to increase an effective data output section.
Recently, the processing speed of semiconductor integrated circuits has been increased and clock signals having a high frequency have been correspondingly used. Accordingly, a DLL circuit should be able to receive a high-frequency external clock signal and output a high-frequency internal clock signal. The higher the frequency of each clock signal that is output through each element in the DLL circuit, the less the wave form is distorted or is not preferably toggled. When each clock signal inside is abnormally generated, the DLL circuit cannot easily perform the primary function of comparing the phases of a reference clock signal and a feedback clock signal and giving a delay time to the reference clock signal on the basis of the compared result. As a result, by using a high-frequency clock signal, the stability of DLL circuit decreases.
Further, by using the high-frequency clock signal, the amount of peak current is increased in the DLL circuit and power consumption is correspondingly increased. The conventional DLL circuit continues comparing phases and delay-controlling using the high-frequency clock signal after delay lock is completed, and accordingly, power consumption is considerably increased. As a result, it is difficult to manufacture a semiconductor integrated circuit that can be operated by low power due to the large amount of power consumption.